The invention relates to elimination of signal distortion in a differential amplifier caused by nonlinear characteristics of the emitter-base junctions and the collector-base junctions of the input transistors of the differential amplifier.
Signal distortion in a differential amplifier circuit is caused mainly by nonlinear characteristics of the input transistors, such as input transistors 2 and 3 in FIG. 1 (which shows a typical differential amplifier circuit stage). An input voltage difference between e.sub.1 and e.sub.2 produces a difference in the emitter-base voltages of transistors 2 and 3, resulting in different currents in those transistors. Since the transistor voltage-current relationship of transistors 2 and 3 is exponential rather than linear, the different currents in transistors 2 and 3 are a major source of distortion. That is, transistors 2 and 3 operate on significantly different parts of their identical, nonlinear current-voltage characteristic curves. This produces distortion in the otherwise linear performance of the differential amplifier stage 1. If the gain of stage 1 can be increased sufficiently, the magnitude of the differential input voltage applied between the bases of transistors 2 and 3 can be reduced, then transistors 2 and 3 operate at nearly the same point on their respective identical voltage-current characteristic curves, and distortion can be greatly reduced.
FIG. 1A shows the transfer curve 7 of the differential amplifier stage 1 of FIG. 1. For small deviations, (i.e., 10-15 millivolts) of .DELTA.e.sub.1 (note that .DELTA.e.sub.1 =e.sub.2 -e.sub.1) from the origin of the transfer curve 7, the curve is quite linear for small applied differential input voltages. The larger the deviation, the greater the distortion. As an example, a large 30 millivolt differential input voltage produces approximately two percent distortion in the output signal e.sub.0, whereas it generally is desirable that the distortion be kept in the 0.1 percent range, which can be achieved if the differential input voltage e.sub.2 -e.sub.1 is less than several millivolts.
Similarly, collector-base voltage swings of input transistors 2 and 3 produce distortion because the identical current-voltage curves of transistors 2 and 3 are quite nonlinear with respect to collector-emitter voltage. Furthermore, the collector junction capacitances of transistors 2 and 3 are highly nonlinear as a function of collector-base voltage. Curve 8 in FIG. 1B shows a nonlinear collector current curve of a transistor such as input transistors 2 and 3. Curve 8 characterizes the "resistive effect" of the input transistors 2 and 3. The slope of the collector-base, current-voltage characteristic of FIG. 1B represents the output impedance of the transistor. At low frequencies, capacitive effects are avoided so the slope of FIG. 1B actually represents the resistive portion of the transistor output impedance. This curve demonstrates a linear region where changes in voltage produce little change in current and this suggests linear operation.
However, added to this low-frequency or resistive output impedance is the capacitive impedance of the collector-base junction capacitance. This capacitance is in parallel with the resistive output impedance and this capacitance also alters collector current. At frequencies above the low frequency domain of FIG. 1B, the capacitive impedance drops with frequency and takes control of the transistor output impedance. This capacitance has a highly nonlinear voltage sensitivity that introduces response nonlinearity.
Curve 9 in FIG. 1C shows the relationship between collector-base junction capacitance and collector-base voltage for transistors 2 and 3. Comparing FIGS. 1B and 1C shows that the nonlinearity of C.sub.CB extends through the C.sub.CB range for which the FIG. 1B is linear. Thus, at other than low frequencies, the output impedance of bipolar transistors is a highly nonlinear function of the collector-base voltage. Due to this nonlinear output impedance, the collector currents in FIG. 1 vary nonlinearly as the collector-base voltage varies in order to support an output voltage. Analogous results occur with transistors other than the bipolar type illustrated here.
To eliminate distortion, it is desirable to eliminate or "balance" voltage swings on the emitter-base junctions and collector-base junctions of input transistors 2 and 3. Stated differently, it is desirable to simultaneously maintain like voltages on like junctions during circuit operation.
In the past, the general approach to solving the above problems of the prior art has been to compensate the distortion by generating counteracting nonlinear signals. U.S. Pat. No. 4,146,844 addresses the problem of distortion associated with the emitter-base junctions of input transistors of a differential amplifier. The nonlinearity associated with the base-emitter voltages of transistors 70 and 72 of U.S. Pat. No. 4,146,844 follows the general transfer curve of FIG. 1A which, however, is modified by the presence by emitter degeneration resistance 75, which extends the linear range of the transfer response. To compensate for the nonlinearity, U.S. Pat. No. 4,146,844 provides two additional transistors 100 and 102 connected so as to develop a nonlinearity that is opposite in shape to that generated by transistors 70 and 72 and then sum the counteracting distortion signals with those produced by nonlinearities of transistors 70 and 72. Transistors 100 and 102 of U.S. Pat. No. 4,146,844 sense signals from both sides of the differential stage by virtue of cross-coupling resistors 116 and 117 and input resistors 115 and 118. However this technique is difficult to implement because of the difficulty of generating a nonlinearity exactly equal and opposite to that of the one to be compensated for. (It should be appreciated that any compensation technique is always inherently limited by the degree to which the manufacturing process can control the matching of components, such as resistors. Our experience is that compensation techniques can reduce signal distortion by a factor of about 10.)
U.S. Pat. No. 4,692,712 discloses compensating for effects of nonlinear junction capacitances of input transistors 2 and 3 and the nonlinear output resistances of transistors 2 and 3. Input transistors Q.sub.1 and Q.sub.2 have nonlinear capacitance and nonlinear output resistance characteristics due to their different collector-base voltages. This results in distortion errors in their respective collector currents. In U.S. Pat. No. 4,692,712, additional transistors Q.sub.7 and Q.sub.8 are provided to match input transistors Q.sub.1 and Q.sub.2, respectively. These transistors are connected so that Q.sub.7 and Q.sub.8 experience the same collector-base voltage swings as transistors Q.sub.1 and Q.sub.2, respectively. The collector currents of Q.sub.7 and Q.sub.8 are cross-coupled to the collectors of Q.sub.2 and Q.sub.1, respectively, so that a nonlinear variation in the collector current of Q.sub.2 is replicated in the collector current of Q.sub.1, and vice versa. As in most compensation schemes, this one depends on the accuracy of matching resistors and other components in a practical integrated circuit manufacturing process.
Perhaps the closest prior art is U.S. Pat. No. 4,897,611. This reference attempts to eliminate the source of nonlinear signal distortion, rather than compensate for it. However, its general approach is distinctly different in two ways from the approach of the present invention. This reference uses positive feedback to create a signal that will remove the gain error signal of a differential amplifier stage. The first differential stage serves as a voltage to current converter. The resulting differential currents are transmitted through cascode devices to input FETs of the second stage in which positive feedback is provided by Q.sub.24 within the second differential stage (which is nested within the first). The nested differential stage is configured so as to monitor any voltage difference between the drain of Q.sub.13 and the drain of Q.sub.11. The current in the drain of Q.sub.24 is conducted to the opposite side of the nested differential stage. Q.sub.23 and Q.sub.24 receive the same input signal, but conduct currents to opposite sides of the differential stage, the drain of Q.sub.24 thereby providing positive feedback. That causes the right side of the nested differential stage to track the left side. The voltage on the drain of Q.sub.13 tracks with the voltage on the drain of Q.sub.11, so any changes in voltage caused by junction capacitances of Q.sub.11 will be tracked by changes in junction capacitance of Q.sub.13.
The stated objective of U.S. Pat. No. 4,897,611 is a differential stage with significantly improved voltage gain. Such gain is also achieved in the course of the operation described above. It is achieved by forcing the differential output of the stage to near zero voltage without reducing the single-ended output voltage. The positive feedback forces the drain voltages of Q.sub.11 and Q.sub.13 to track, and this action reduces the differential output voltage of the stage almost to zero. Yet, the single-ended output voltage of the stage remains available to be used as the final circuit output. With near zero differential output voltage, very little differential input voltage is required for the stage. By retaining the single-ended output, a high gain results between the small differential input signal and the single-ended output voltage. This high gain theoretically equals the product of the gains of the two differential stages.
However, positive feedback is likely to cause circuit oscillations and latching. To safely use positive feedback, it is necessary to back off considerably from theoretical design limits. Even when oscillation and latching does not occur, signal responses tend to be characterized by "ringing" or decaying oscillations before output signal levels stabilize. This technique effectively reduces the distortion associated with junction capacitances of Q.sub.13, Q.sub.11, Q.sub.20, and Q.sub.17, which are large output devices subject to large signal swings and are the primary cause of distortion.
U.S. Pat. No. 4,743,861 discloses techniques for accomplishing broader bandwidth by use of emitter degeneration resistors in a differential circuit stage nested within another differential circuit stage, and providing feedback from the nested differential stage to the emitter circuitry of the primary differential stage to produce a high frequency zero in the frequency response of the circuit.
There remains an unmet need for an improved technique for reducing distortion in differential amplifier circuits due to nonlinearities in the input transistors thereof.